DATEOptimize edge AI processing through innovative compilation techniques

Shreya Alladi, Alexandre Lopoukhine, Georgios Alexandris, Andrea Nardi-Dei, Ravikiran Ravindranath Reddy, Christos P. Lamprakos, Panagiotis Chaidos, Alexis Maras, Alberto Ros, Tobias Grosser, Sotirios Xydis, Dimitrios Soudris, Marc Geilen, Sander Stuijk, Henk Corporaal, Alexandra Jimborean, 2026

Heterogeneous architectures became a compelling choice for edge processors executing complex DNN workloads, as they provide an ideal blend of openness, customization, energy-efficient heterogeneity, and scalable performance. Compiler optimization for DNNs on heterogeneous System-on-Chip (SoC) architectures however, must navigate complex hardware-software co-design, data movement minimization, aggressive parallelism exploitation, and advanced static/dynamic code transformations to deliver high performance and energy efficiency.This paper presents a novel compiler ecosystem for highly heterogeneous SoCs with multiple back-end targets, spanning from typical CPUs, to programmable RISC-V clusters and up to dedicated and reconfigurable accelerators. It puts together static analysis, optimization, and scheduling infrastructure to overcome the limitations of current state-of-the-art tools for heterogeneous edge AI processors. Our compilation pipeline introduces several innovative features: (1) an automatic end-to-end flow for RISC-V-based platforms, (2) efficient data layout remapping (reducing memory footprint by 35% on average) and recognition of complex ternary reductions for auto-vectorization, (3) code layout adaptation for hardware simplification, (4) a novel MLIR-based RISC-V backend supporting optimized matrix-multiplication micro-kernels that reach 90% of peak performance, (5) periodic scheduling capabilities for layer-fused CNNs, and (6) automated mapping and scheduling onto heterogeneous CGRA templates for advanced parallel kernel execution, delivering 33% higher energy efficiency than the scalar implementation and up to 3.6× higher performance. These advances enable hardware-aware compilation that reduces manual optimization effort, lowers energy consumption through memory and computation optimization, and minimizes memory footprint and data transfers.

Publisher

@inproceedings{alladi2026edgeai,
  author = {Alladi, Shreya and Lopoukhine, Alexandre and Alexandris, Georgios and Nardi-Dei, Andrea and Reddy, Ravikiran Ravindranath and Lamprakos, Christos P. and Chaidos, Panagiotis and Maras, Alexis and Ros, Alberto and Grosser, Tobias and Xydis, Sotirios and Soudris, Dimitrios and Geilen, Marc and Stuijk, Sander and Corporaal, Henk and Jimborean, Alexandra},
  title = {{Optimize edge AI processing through innovative compilation techniques}},
  booktitle = {2026 Design, Automation \& Test in Europe Conference (DATE)},
  series = {DATE},
  year = {2026},
  month = {4},
  publisher = {IEEE},
  doi = {10.23919/date69613.2026.11539616},
  url = {https://doi.org/10.23919/date69613.2026.11539616}
}