CGOA Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis, Anton Lydike, Josse Van Delm, Alban Dutilleul, Luca Benini, Marian Verhelst, Tobias Grosser, 2025

High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to deep neural networks (DNNs). While higher-level optimizations for DNNs are offered by numerous compilers (e.g., MLIR, TVM, OpenXLA), performance-critical micro-kernels are left to specialized code generators or handwritten assembly. Even though widely-adopted compilers (e.g., LLVM, GCC) offer tuned backends, their CPU-focused input abstraction, unstructured intermediate representation (IR) and general-purpose best-effort design inhibit tailored code generation for innovative hardware. We think it is time to widen the classical hourglass backend and embrace progressive lowering across a diverse set of structured abstractions to bring domain-specific code generation to compiler backends. We demonstrate this concept by implementing a custom backend for a RISC-V-based accelerator with hardware loops and streaming registers, leveraging knowledge about the hardware at levels of abstraction that match its custom instruction set architecture (ISA). We use incremental register allocation over structured IRs, while dropping classical spilling heuristics, and show up to 90% floating-point unit (FPU) utilization across key DNN kernels. By breaking the backend hourglass model, we reopen the path from domain-specific abstractions to specialized hardware.

Publisher

@inproceedings{lopoukhineMultilevelCompilerBackend2025,
  author = {Lopoukhine, Alexandre and Ficarelli, Federico and Vasiladiotis, Christos and Lydike, Anton and Van Delm, Josse and Dutilleul, Alban and Benini, Luca and Verhelst, Marian and Grosser, Tobias},
  title = {A {{Multi-level Compiler Backend}} for {{Accelerated Micro-kernels Targeting RISC-V ISA Extensions}}},
  booktitle = {Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization},
  series = {CGO},
  pages = {163--178},
  year = {2025},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  doi = {10.1145/3696443.3708952},
  url = {https://dl.acm.org/doi/10.1145/3696443.3708952},
  isbn = {979-8-4007-1275-3}
}